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triple-channel digital isolator with programmable default output adum1310 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features pb-free, 16-lead, wide body soic package low power operation 5 v operation 1.0 ma per channel max @ 0 mbps to 2 mbps 3.5 ma per channel max @ 10 mbps 3 v operation 0.7 ma per channel max @ 0 mbps to 2 mbps 2.1 ma per channel max @ 10 mbps 3 v/5 v level translation high temperature operation: 105c up to 10 mbps data rate (nrz) programmable default output state safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din en 60747-5-2 (vde 0884 part 2): 2003-01 din en 60950 (vde 0805): 2001-12; en 60950: 2000 v iorm = 560 v peak applications general-purpose, unidirectional, multichannel isolation general description the adum1310 1 is a unidirectional, triple-channel digital isolator based on analog devices, inc. i coupler? technology. combining high speed cmos and monolithic coreless trans- former technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. by avoiding the use of leds and photodiodes, i coupler devices remove the design difficulties commonly associated with optocouplers. the typical concerns that arise with opto- couplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple i coupler digital interfaces and stable performance characteristics. the need for external drivers and other discretes is eliminated with these i coupler products. furthermore, i coupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates. the adum1310 isolator provides three independent isolation channels at data rates up to 10 mbps. it operates with the supply voltage of either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. this product also has a default output control pin. this allows the user to define the logic state the outputs are to adopt in the absence of the input v dd1 power. unlike other optocoupler alternatives, the adum1310 has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. functional block diagram encode decode encode decode encode decode v dd1 a dum1310 gnd 1 v ia v ib v ic nc disable gnd 1 v dd2 gnd 2 v oa v ob v oc nc ctrl gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc = no connect 04904-001 figure 1. 1 protected by u.s. patents 5,952,849; 6,873,065; and other pending patents.
adum1310 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics5 v operation................................ 3 electrical characteristics3 v operation................................ 4 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation....................................................................................... 5 package characteristics ............................................................... 7 insulation and safety-related specifications............................ 7 din en 60747-5-2 (vde 0884 part 2) insulation characteristics .............................................................................. 8 recommended operating conditions ...................................... 8 absolute maximum ratings ............................................................9 regulatory information................................................................9 esd caution...................................................................................9 pin configuration and function descriptions........................... 10 typical performance characteristics ........................................... 11 application information................................................................ 12 pc board layout ........................................................................ 12 propagation delay-related parameters................................... 12 dc correctness and magnetic field immunity........................... 12 power consumption .................................................................. 13 power-up/power-down considerations ................................ 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 10/06rev. d to rev. e removed adum1410 ........................................................universal updated format..................................................................universal change to figure 3 ......................................................................... 10 changes to table 10........................................................................ 10 changes to application information ........................................... 12 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 3/06rev. c to rev. d added note 1 and changes to figure 2......................................... 1 changes to absolute maximum ratings ..................................... 11 11/05rev. spb to rev. c 5/05rev. spa to rev. spb changes to table 6.............................................................................9 10/04data sheet changed from rev. sp0 to rev. spa changes to table 5.............................................................................9 6/04revision sp0: initial version
adum1310 rev. e | page 3 of 16 specifications electrical characteristics5 v operation 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v; all voltages are relative to their respective ground. table 1. parameter symbol min typ max unit test conditions dc specifications total supply current, three channels 1 v dd1 supply current, quiescent i dd1 (q) 2.4 3.2 ma v ia = v ib = v ic = v id = 0 v dd2 supply current, quiescent i dd2 (q) 1.2 1.6 ma v ia = v ib = v ic = v id = 0 v dd1 supply current, 10 mbps data rate i dd1 (10) 6.6 9.0 ma 5 mhz logic signal frequency v dd2 supply current, 10 mbps data rate i dd2 (10) 2.1 3.0 ma 5 mhz logic signal frequency input currents i ia , i ib , i ic , i id , i ctrl , i disable C10 +0.01 +10 a 0 v ia , v ib , v ic , v id , v disable v dd1 , 0 v ctrl v dd2 logic high input threshold v ih 2.0 v logic low input threshold v il 0.8 v logic high output voltages v oah , v obh , v och , v odh v dd1, v dd2 ? 0.4 4.8 v i ox = C4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = +4 ma, v ix = v ixl switching specifications minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh C t phl | 4 pwd 5 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 30 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd 5 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immuni ty at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input enable time 8 t enable 2.0 s v ia , v ib , v ic , v id = 0 or v dd1 input disable time 8 t disable 5.0 s v ia , v ib , v ic , v id = 0 or v dd1 input dynamic supply current per channel 9 i ddi (d) 0.19 ma/mbps output dynamic supply current per channel 9 i ddo (d) 0.05 ma/mbps 1 supply current values are for all four ch annels combined running at identical data rates. output supply current values are spe cified with no output load present. the supply current associated with an individual ch annel operating at a given data rate can be calculated as de scribed in the power consumption section. see figure 4 through figure 6 for information on the per-ch annel supply current as a function of the data rate for unload ed and loaded condi tions. see figure 7 and figure 8 for total i dd1 and i dd2 supply currents as a function of the data rate for the adum1310 ch annel configurations. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure, supply voltages, and output load within the recommended operating conditions. 6 channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 input enable time is the duration from when v disable is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. if an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. input disable time is the d uration from when v disable is set high until the output states are guaranteed to re ach their programmed ou tput levels, as determined by the ctrl logic state (see tabl e 9). 9 dynamic supply current is the incremental amo unt of supply current required for a 1 m bps increase in the signal data rate. see figure 4 through figure 6 for information on the per-channel su pply current as a function of the data rate for unloaded and loaded co nditions. see the power consumption section for guidance on calculating the per-channel su pply current for a given data rate.
adum1310 rev. e | page 4 of 16 electrical characteristics3 v operation 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v; all voltages are relative to their respective ground. table 2. parameter symbol min typ max unit test conditions dc specifications adum1310, total supply current, three channels 1 v dd1 supply current, quiescent i dd1 (q) 1.2 1.6 ma v ia = v ib = v ic = v id = 0 v dd2 supply current, quiescent i dd2 (q) 0.8 1.0 ma v ia = v ib = v ic = v id = 0 v dd1 supply current, 10 mbps data rate i dd1 (10) 3.4 4.9 ma 5 mhz logic signal frequency v dd2 supply current, 10 mbps data rate i dd2 (10) 1.1 1.3 ma 5 mhz logic signal frequency input currents i ia , i ib , i ic , i id , i ctrl , i disable C10 +0.01 +10 a 0 v ia , v ib , v ic , v id , v disable v dd1 , 0 v ctrl v dd2 logic high input threshold v ih 1.6 v logic low input threshold v il 0.4 v logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 C 0.4 2.8 v i ox = C4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = +4 ma, v ix = v ixl switching specifications minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh C t phl | 4 pwd 5 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew (equal temperature) 5 t psk 30 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd 5 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input enable time 8 t enable 2.0 s v ia , v ib , v ic , v id = 0 or v dd1 input disable time 8 t disable 5.0 s v ia , v ib , v ic , v id = 0 or v dd1 input dynamic supply current per channel 9 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 9 i ddo (d) 0.03 ma/mbps 1 supply current values are for all channels combined running at identical data rates. output supply current values are specifie d with no output load present. the supply current associated with an individu al channel operating at a given data rate can be calculated as described in the power consum ption section. see figure 4 through figure 6 for information on the per-channel supply current as a function of the da ta rate for unloaded an d loaded conditions. s ee figure 7 through figure 8 for total i dd1 and i dd2 supply currents as a function of the data rate. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure, supply voltages, and output load within the recommended operating conditions. 6 channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 input enable time is the duration from when v disable is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. if an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. input disable time is the d uration from when v disable is set high until the output states are guaranteed to re ach their programmed ou tput levels, as determined by the ctrl logic state (see tabl e 9). 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 4 through figure 6 for information on the per-channel supply current as a functi on of the data rate for un loaded and loaded conditions . see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
adum1310 rev. e | page 5 of 16 electrical characteristicsmixe d 5 v/3 v or 3 v/5 v operation 5 v/3 v operation 1 : 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v; 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v; or v dd1 = 5 v, v dd2 = 3.0 v. table 3. parameter symbol min typ max unit test conditions dc specifications adum1310, total supp ly current, three channels 2 v dd1 supply current, quiescent i ddi (q) 5 v/3 v operation 2.4 3.2 ma v ia = v ib = v ic = v id = 0 3 v/5 v operation 1.2 1.6 ma v ia = v ib = v ic = v id = 0 v dd2 supply current, quiescent i ddo (q) 5 v/3 v operation 0.8 1.0 ma v ia = v ib = v ic = v id = 0 3 v/5 v operation 1.2 1.6 ma v ia = v ib = v ic = v id = 0 v dd1 supply current, 10 mbps data rate i dd1 (10) 5 v/3 v operation 6.5 8.2 ma 5 mhz logic signal frequency 3 v/5 v operation 3.4 4.9 ma 5 mhz logic signal frequency v dd2 supply current, 10 mbps data rate i dd2 (10) 5 v/3 v operation 1.1 1.3 ma 5 mhz logic signal frequency 3 v/5 v operation 1.9 2.2 ma 5 mhz logic signal frequency input currents i ia , i ib , i ic , i id , i ctrl , i disable C10 +0.01 +10 a 0 v ia , v ib , v ic , v id , v disable v dd1 , 0 v ctrl v dd2 logic high input threshold v ih 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v logic high output voltages v oah , v obh , v och , v odh v dd1 /v dd2 ? 0.4 v dd1 /v dd2 ? 0.2 v i ox = C4 a, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = +4 a, v ix = v ixl switching specifications minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 30 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh C t phl | 5 pwd 5 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 30 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd 5 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 5 v/3 v operation 3.0 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v
adum1310 rev. e | page 6 of 16 parameter symbol min typ max unit test conditions refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input enable time 9 t enable 2.0 s v ia , v ib , v ic , v id = 0 or v dd1 input disable time 9 t disable 5.0 s v ia , v ib , v ic , v id = 0 or v dd1 input dynamic supply current per channel 10 i ddi (d) 5 v/3 v operation 0.19 ma/mbps 3 v/5 v operation 0.10 ma/mbps output dynamic supply current per channel 10 i ddo (d) 5 v/3 v operation 0.03 ma/mbps 3 v/5 v operation 0.05 ma/mbps 1 all voltages are relative to their respective ground. 2 supply current values are for all channels combined running at identical data rates. output supply current values are specifie d with no output load present. the supply current associated with an individu al channel operating at a given data rate can be calculated as described in the power consum ption section. see figure 4 through figure 6 for information on the per-channel supply current as a function of the da ta rate for unloaded an d loaded conditions. s ee figure 7 through figure 8 for total i dd1 and i dd2 supply currents as a function of the data rate. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure, supply voltages, and output load within the recommended operating conditions. 7 channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 input enable time is the duration from when v disable is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. if an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. input disable time is the d uration from when v disable is set high until the output states are guaranteed to re ach their programmed ou tput levels, as determined by the ctrl logic state (see trut h table C table 9). 10 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 4 through figure 6 for information on the per-channel supply current as a functi on of the data rate for un loaded and loaded conditions . see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
adum1310 rev. e | page 7 of 16 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 2 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 33 c/w thermocouple located at center of package underside ic junction-to-case thermal resistance, side 2 jco 28 c/w thermocouple located at center of package underside 1 device considered a 2-terminal device. pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8 shorted together and pin 9, pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, and pin 16 shorted together. 2 input capacitance is from any input data pin to ground. insulation and safety-related specifications table 5. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.7 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
adum1310 rev. e | page 8 of 16 din en 60747-5-2 (vde 0884 part 2) insulation characteristics the adum1310 isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by means of protective circuits. the * marking on packages denotes din en 60747-5-2 approval for 560 v peak working voltage. category i through category iv listed in the char acteristic column are per din en 60747-5-2 definition. table 6. description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v pr 1050 v peak v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge <5 pc input-to-output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge <5 pc 896 v peak after input and/or safety test subgroup 2/3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge <5 pc 672 v peak highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety-limiting values (maximum value allowed in the event of a failure; see figure 2 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s , v io = 500 v r s >10 9 case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 04904-003 figure 2. thermal derating curve, dependence of safety-limiting values with case temperature per din en 60747-5-2 recommended operat ing conditions table 7. parameter symbol min max unit operating temperature t a C40 +105 c supply voltages 1 v dd1 , v dd2 2.7 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. see the dc correctness and magnetic field immunity section for informati on on immunity to external magnetic fields.
adum1310 rev. e | page 9 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 8. parameter rating storage temperature C65c to +150c ambient operating temperature C40c to +105c supply voltages 1 C0.5 v to +6.5 v input voltage 1, 2 C0.5 v to v ddi + 0.5 v output voltage 1, 2 C0.5 v ddo + 0.5 v to v ddo + 0.5 v average output current per pin 3 side 1 C18 ma to +18 ma side 2 C22 ma to +22 ma common-mode transients 4 C100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. 3 see figure 2 for maximum rated current values for various temperatures. 4 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the absolu te maximum ratings can cause latch- up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. regulatory information in accordance with ul1577, each adum1310 is proof tested by applying an insulation test voltage 3000 v rms for 1 second (current leakage detection limit = 5 a). in accordance with din en 60747-5-2, each adum1310 is proof tested by applying an insulation test voltage 1050 v peak for 1 second (partial discharge detection limit = 5 pc). the adum1310 is approved by the following organizations: ul: recognized under 1577 component recognition program. csa: approved under csa component acceptance notice #5a. vde: certified according to din en 60747-5-2 (vde 0884 part 2): 2003-01, and din en 60950 (vde 0805): 2001-12; en 60950: 2000. esd caution table 9. truth table (positive logic) v ix input 1 ctrl input v disable state v dd1 state 1 v dd2 state 1 v ox output 1 notes h x l or nc powered powered h no rmal operation, data is high. l x l or nc powered powered l no rmal operation, data is low. x h or nc h x powered h inputs disabled. outputs are in the default state as determined by ctrl. x l h x powered l inputs disabled. outputs are in the default state as determined by ctrl. x h or nc x unpowered powered h input unpowered. outputs are in the de fault state as determined by ctrl. outputs return to input state within 1 s of v dd1 power restoration. see the power-up/power-down considerations section for more details. x l x unpowered powered l input unpowered. outputs are in the de fault state as determined by ctrl. outputs return to input state within 1 s of v dd1 power restoration. see the power-up/power-down considerations section for more details. x x x powered unpowered z output unpowered. output pins are in high impedance state. outputs return to input state within 1 s of v dd2 power restoration. see the power-up/power-down considerations section for more details. 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d).
adum1310 rev. e | page 10 of 16 pin configuration and fu nction descriptions 04904-004 v dd1 1 gnd 1 * 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 nc 6 nc 11 disable 7 ctrl 10 gnd 1 * 8 gnd 2 * 9 nc = no connect adum1310 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. figure 3. pin configuration table 10. adum1310 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected; connecting both pins to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 nc no connect. 7 disable input disable. disables the isolator inputs and re freshes. outputs take on logic state determined by ctrl. 8 gnd 1 ground 1. ground reference for isolator side 1. pin 8 and pin 2 are internally connected; connecting both pins to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected; connecting both pins to gnd 2 is recommended. 10 ctrl default output control. controls the logic state th e outputs take on when th e input power is off. v oa , v ob , and v oc outputs are high when ctrl is high or disconnected and v dd1 is off. v oa , v ob , and v oc outputs are low when ctrl is low and v dd1 is off. when v dd1 power is on, this pin has no effect. 11 nc no connect. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected; connecting both pins to gnd 2 is recommended. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum1310 rev. e | page 11 of 16 typical performance characteristics 5v 3v data rate (mbps) current/channel (ma) 2.5 2.0 1.5 1.0 0 0.5 04 26 8 1 0 04904-006 figure 4. typical supply current per input channel vs. data rate for 5 v and 3 v operation 5v 3v data rate (mbps) current/channel (ma) 0.7 0.5 0.6 0.4 0.2 0.1 0.3 0 04 26 8 1 0 04904-007 figure 5. typical supply current per output channel vs. data rate for 5 v and 3 v operation (no output load) 5v 3v data rate (mbps) current/channel (ma) 1.2 0.8 1.0 0.4 0.2 0.6 0 04 26 8 1 0 04904-008 figure 6. typical supply current per output channel vs. data rate for 5 v and 3 v operation (15 pf output load) 5v 3v data rate (mbps) current (ma) 7 5 6 3 2 1 4 0 04 26 8 1 0 04904-009 figure 7. typical adum1310 v dd1 supply current vs. data rate for 5 v and 3 v operation 5v 3v data rate (mbps) current (ma) 2.5 2.0 1.0 0.5 1.5 0 04 26 8 1 0 04904-010 figure 8. typical adum1310 v dd2 supply current vs. data rate for 5 v and 3 v operation
adum1310 rev. e | page 12 of 16 application information pc board layout the adum1310 digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 9 ). bypass capacitors are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypassing between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless the ground pair on each package side is connected close to the package. v dd1 gnd 1 v ia v ib v ic nc disable gnd 1 v dd2 gnd 2 v oa v ob v oc nc ctrl gnd 2 nc = no connect 04904-013 figure 9. recommended printed circuit board layout propagation delay-related parameters propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. the input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. input ( v ix ) output (v ox ) t plh t phl 50% 50% 0 4904-014 figure 10. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signals timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum1310 component. propagation delay skew refers to the maximum amount the propagation delay differs among multiple adum1310 components operated under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable, and is, therefore, either set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than 2 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default state (see table 9 ) by the watchdog timer circuit. the magnetic field immunity of the adum1310 is determined by the changing magnetic field which induces a voltage in the trans- formers receiving coil large enough to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the adum1310s 3 v operating condition is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold of about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt ) r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm).
adum1310 rev. e | page 13 of 16 given the geometry of the receiving coil in the adum1310 and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. the result is shown in figure 11 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 1 1 100m 100k 0 4904-015 figure 11. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is approximately 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum1310 transformers. figure 12 expresses these allowable current mag- nitudes as a function of frequency for selected dis tances. as can be seen, the adum1310 is extremely immune and can be affected only by extremely large currents operated at high fre- quency, very close to the component. for the 1 mhz example noted, a 0.5 ka current needed to be placed 5 mm away from the adum1310 to affect the operation of the component. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 04904-016 figure 12. maximum allowable current for various current-to-adum1310 spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum1310 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. for each input channel, the supply current is given by i ddi = i ddi (q) f 0.5 f r i ddi = i ddi (d) (2 f C f r ) + i ddi (q) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo (q) f 0.5 f r i ddo = ( i ddo (d) + c l v ddo ) (2 f C f r ) + i ddo (q) f 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (hz, half of the input data rate, nrz signaling). f r is the input stage refresh rate (bps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to i dd1 and i dd2 are calculated and totaled. figure 4 and figure 5 provide per-channel supply currents as a function of the data rate for an unloaded output condition. figure 6 provides per- channel supply current as a function of the data rate for a 15 pf output condition. figure 7 through figure 8 provide total i dd1 and i dd2 supply current as a function of the data rate for the adum1310.
adum1310 rev. e | page 14 of 16 power-up/power-down considerations given that the adum1310 has separa te supplies on either side of the isolation barrier, the power-up and power-down characteristics relative to each supply voltage need to be considered individually. as shown in table 9 , when v dd1 input power is off, the adum1310 outputs take on a default condition as determined by the state of the ctrl pin. as the v dd1 supply is increased/decreased, the output of each channel transitions from/to the default condition to/from the state matching its respective signals (see figure 13 and figure 14 ). v dd1 output data output data ctrl = high or nc ctrl = low v dd1 2v (typ) 0 4904-017 figure 13. v dd1 power-up/power-down characteristics, input data = high v dd1 output data output data ctrl = high or nc ctrl = low v dd1 2v (typ) 0 4904-018 figure 14. v dd1 power-up/power-down characteristics, input data = low when v dd1 crosses the threshold for activating the refresh circuit (approximately 2 v), there can be a delay of up to 2 s before the output is updated to the correct state, depending on the timing of the next refresh pulse. when v dd1 is reduced from an on state below the 2 v threshold, there can be a delay of up to 5 s before the output takes on its default state determined by the ctrl signal. this corresponds to the duration that the watchdog timer circuit at the input is designed to wait before triggering an output default state. when the v dd2 output supply is below the level at which the adum1310 output transistors are biased (about 1 v), the outputs take on a high impedance state. when v dd2 is above a value of about 2 v, each channel output takes on a state matching that of its respective input. between the values of 1 v and 2 v, the outputs are set low. this behavior is shown in figure 15 and figure 16 . v dd2 output data high impedance high impedance 2v (typ) 04904-019 figure 15. v dd2 power-up/power-down characteristics, input data = high v dd2 output data high impedance high impedance 2v (typ) 04904-020 figure 16. v dd2 power-up/power-down characteristics, input data = low
adum1310 rev. e | page 15 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 060606-a 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 5 0 ( 0 . 0 1 9 7 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 45 figure 17. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model number of channels maximum data rate (mbps) temperature range package description package option adum1310brwz 1 3 10 ?40c to +105c 16-lead wide body soic_w rw-16 ADUM1310BRWZ-RL 1 , 2 3 10 ?40c to +105c 16-lead wide body soic_w rw-16 1 z = pb-free part. 2 the addition of an -rl suff ix designates a 13-inch (1,000 units) tape and reel option.
adum1310 rev. e | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04904-0-10/06(e)

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